Multi-target, multi-rate deploy

One model, several destinations — each generated from its own subsystem, in its own language, at its own rate.

A target is a small contract

You create targets on the Deploy To Hardware panel, and each one names five things:

  • Target name — what you call it;
  • Scripting — which of the ten languages;
  • Verification — None, Output Gates Only, Output Gates and Sink Blocks, or Strict (all signals);
  • Source subsystem — which level of the model this target is generated from, defaulting to the whole model;
  • Target path — where the folder is written.

Targets are saved beside the project, so they come back with it. Press Deploy on one, or Deploy All to send every target out together.

Two rates, one model
The Digital PID Loop diagram, with one controller held at a quarter of the other's rate The Digital PID Loop diagram, with one controller held at a quarter of the other's rate
Two discrete PID loops, one held at a quarter of the other's rate so the sampling shows. A model like this deploys as several targets — one per subsystem that is uniform in rate.

How multi-rate models ship

A single generated core advances at one rate — that is what "one call, one sample" means. So a model whose parts run at different rates is deployed as several targets, each pointed at a subsystem that is uniform in rate, each generated at that subsystem's rate. A slow supervisory loop and a fast inner loop become two deployables, in whichever languages each destination needs: the inner loop to C or HDL, the supervisor to Structured Text or Python.

If a target's subtree is not uniform in rate, the export says so and stops, rather than picking a rate for you.

Deploy target · Scripting
A deploy target's Scripting list open, showing all ten export languages A deploy target's Scripting list open, showing all ten export languages
Each target picks its own language from the same list — Python, MATLAB, Java, Rust, C++, C, SystemVerilog, Verilog, VHDL and PLC Structured Text — so one model can feed a microcontroller, an FPGA and a test rig at once.

Different languages from the same model

Nothing requires two targets to share a language. The same diagram can produce a C core for a microcontroller, a VHDL entity for the FPGA beside it, and a Python core for the test rig — from one source of truth, all verified the same way.

See also: Code export  ·  Verification

Get started

See it run on your own model.

Download the application from the customer portal, or read the documentation first — the manual, every block with its measured response, and the full command reference are public.