Code export
Ten languages, one shape: a core that advances the model by exactly one sample per call, a testbench that drives it, and a build file so the folder compiles as it is.
What every export contains
- a deployable core — one call advances the model by one sample;
- a testbench that drives it across the simulation window;
- a build file, where the language has one.
Inside the core: params that stay tunable after export (change a gain without
regenerating), one fixed-size signal per output port, inputs you set before each
call, and persistent block state. Storage is fixed-size and nothing is allocated at run
time. Software targets compute in double — LREAL in Structured Text.
The ten targets
| Target | Deploy writes | One call advances one sample |
|---|---|---|
| C | <name>_deployableCore.h/.c, testbench, CMakeLists.txt | DeployableCore_init(&core), then execute_blocks(&core) |
| C++ | <name>_deployableCore.hpp, testbench, CMakeLists.txt | struct DeployableCore · execute_blocks() |
| Rust | <name>_deployableCore.rs, testbench, Cargo.toml | execute_blocks(&mut self) |
| Python | <name>_deployableCore.py, testbench | execute_blocks() · needs numpy |
| MATLAB | <name>_deployableCore.m, testbench | classdef … < handle · core.execute_blocks() |
| Java | <name>_deployableCore.java, testbench | executeBlocks() |
| VHDL | icore_pkg.vhd, entity, testbench, Makefile (GHDL) | one rising clk edge |
| Verilog | icore_defs.vh, module, testbench, Makefile (Icarus) | one clk edge |
| SystemVerilog | icore_defs.svh, module, testbench, Makefile (Icarus) | one clk edge |
| PLC · ST | <name>_deployableCore.st, testbench | FUNCTION_BLOCK FB_<name> — one scan |
Which blocks support which target
Measured over the 308 library blocks: 306 support all ten targets. The two exceptions are the user-code blocks — the C block exports to C, the Python block to Python — which is what those blocks mean. Each block's own page names the targets it implements, and that list is checked against its code on every documentation build.
The rules the export enforces
- Fixed-step or discrete solver only. The generated core has no notion of a variable step, so a variable-step model is refused rather than quietly approximated.
- One sampling rate across the exported subtree. A model with several rates deploys as several targets — see multi-target deploy.
- The model name becomes the identifier stem, sanitized to what VHDL and Structured Text will accept — they are the strictest of the ten and set the rule for all of them.
Fixed point on the HDL targets
VHDL, Verilog and SystemVerilog carry every signal in Q16.16: sixteen integer bits including sign, sixteen fractional — a range of about ±32768 and a step of 1.5e-5. Their residual against the simulation is therefore set by the number format, not by the generator.
See also: Verification · Multi-target, multi-rate deploy
See it run on your own model.
Download the application from the customer portal, or read the documentation first — the manual, every block with its measured response, and the full command reference are public.